Dynamic random access memories (DRAMs) are a widely used form of semiconductor memory. DRAMs are composed of a memory cell array and peripheral circuitry. Each memory cell array is formed of a plurality of memory cells for storing information. Typical memory cells are formed with a transistor for accessing a capacitor that stores charge. Of primary concern is maximizing the storage capacitance of each memory cell capacitor. This need is particularly acute in light of the demand for high density DRAMs, without increasing the chip area required to form the cell and, preferably, allowing a decrease in the chip area per cell.
One way to achieve greater capacitance per cell is to increase the surface area of the capacitor electrodes without increasing the respective cell area. As can be seen from the following equation, capacitance, C, is roughly determined by the thickness of the capacitor insulator (t.sub.ox), the surface area of the capacitor electrodes (A), and the dielectric constant of the capacitor insulator (.epsilon.). EQU C=(.epsilon..multidot.A)/t.sub.ox
Increasing thc surface area of the capacitor electrodes by forming the storage capacitor in a container like shape is well known in the art. To further increase circuit density in DRAMs stacked capacitors are used. These capacitors are actually stacked on top of the substrate, which may or may not include access devices. Two or more layers of a conductive material called electrodes formed of polysilicon or poly are deposited over the substrate with dielectric layers sandwiched between each electrode.
U.S. Pat. No. 5,340,765 to Dennison et al., herein incorporated by reference, describes a method for further increasing the surface area of a bottom electrode of such capacitors by forming the electrode surfaces with hemispherical grained polysilicon (HSG). First, a portion of an oxide layer covering access circuitry on a semiconductor wafer is removed to form a container. A bottom electrode is then formed by growing an amorphous silicon layer. The amorphous silicon layer is then seeded by flowing silane or disilane at elevated temperatures.
After seeding, the wafer is annealed to form HSG on both sides of the doped silicon layer. Formation of a dielectric layer and top capacitor plate complete the capacitor formation.
While the above method creates a roughened surface on the capacitor electrode plate to increase capacitance per unit area, it can lead to undesired deposits forming on oxide, BPSG or other insulator between structures where silicon is desired to be deposited. Such conductive deposits are referred to as stringers which are caused by residual poly film deposited on oxide surfaces that short nearby storage cells or other structures where it is desired to form the poly film. Further steps, such as etches are then required to eliminate such shorting.
There is a need to form poly films in a selective manner. There is a need to form selective poly films in a manner which reduces the need for further processing steps to remove undesired residual poly films. There is yet a further need to form selective poly films without forming shorts between structures on which the film is desired. There is a further need to form such poly films only where formation of HSG is desired. With the rapid decrease in device size, coupled with the demand for increased performance, a new, efficient technique must be found to provide an increase in the capacitance per unit area in DRAM memory cells without causing shorts between cells.